1. Field of the Invention
The present invention relates to a process for producing an integrated capacitor and to a circuit comprising a capacitor thus produced.
2. Description of the Related Art
Several methods are used to incorporate a capacitor into an integrated electronic circuit. They may be divided into two categories, depending on the position of the capacitor in the circuit.
The methods of the first category result in a capacitor that is located in one of the interconnection levels placed above the substrate that carries the integrated circuit. Capacitors of the MIM (metal-insulator-metal) type are thus produced, for which the electrodes are parallel to the surface of the substrate. Because of this orientation, such an MIM capacitor occupies a large surface portion projected onto the substrate. The resulting footprint makes it more difficult to place metal tracks and vias within the interconnect layers. Correspondingly, the capacitance of such a capacitor is limited by the available area within the interconnect layer. Capacitors whose electrodes are perpendicular to the interconnect layer have also been produced, but their dimensions and their capacitance are limited by the thickness of the interconnect layer, which is of the order of a few microns.
The methods of the second category result in a capacitor located at the surface of the substrate, at the same level as the transistors of the circuit. Capacitors of the MIS (metal-insulator-semiconductor) type fall within this category, but their capacitance is in general quite low. The capacitors used in the fabrication of DRAM memories are also located at the surface of the substrate. They are placed inside trenches formed in the substrate and are obtained from materials deposited in succession in each trench. Their low capacitance is suitable for operation in two states, in which the capacitor is respectively charged or discharged. Furthermore, the production of an electrical connection to the lower electrode of such a DRAM capacitor may be difficult to achieve. It is often obtained by doping a region of the substrate that is in contact with the lower electrode of the capacitor.
U.S. Pat. No. 6,787,836 discloses a process for producing an integrated circuit that makes it possible to produce a capacitor having one of its electrodes at the same metallization level as transistor gates. The capacitor is located between the surface of the substrate and the first interconnect layer. Given that its electrodes are parallel to the surface of the substrate, it has a large footprint thereon, and its capacitance is consequently limited. Furthermore, the process described in that document involves three successive masks. It is therefore particularly lengthy, and a high fabrication efficiency is certainly difficult to achieve.